Dsp Public Peripherals - Texas Instruments OMAP5910 Reference Manual

TI Peripheral Bus Bridges
8.3

DSP Public Peripherals

8.4 DSP/MPU Shared Peripherals
8.5 Peripheral Access Rate
188 DSP Subsystem
Peripherals on the DSP public peripheral bus are considered public
peripherals. These peripherals are directly accessible by the DSP core and
DSP DMA. The MPU core can also access these peripherals through the
MPUI port (see section 9). DSP public peripherals on OMAP5910 and
OMAP5912 include:
Two Multichannel Buffered Serial Ports (McBSP1 and McBSP3)
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Two Multichannel Serial Interfaces (MCSI1 and MCSI2)
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The shared peripherals are connected to both the MPU public peripheral bus
and the DSP public peripheral bus. Connections are achieved via a TI
peripheral bus switch, which must be configured to allow MPU or DSP access.
The other shared peripherals have permanent connections to both public
peripheral buses, although read and write accesses to each peripheral
register may differ.
DSP/MPU shared peripherals on OMAP5910 and OMAP5912 include:
Mailbox registers
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Three Universal Asynchronous Receiver/Transmitter modules (UART1,
-
UART2, and UART3)
General-purpose I/O (GPIO)
-
OMAP5912 also includes the following DSP/MPU shared peripherals:
Eight general purpose timers
-
Serial Port Interface (SPI)
-
2
I C master/slave interface
-
Multichannel Buffered Serial Port 2 (McBSP2)
-
Multimedia Card/Secure Digital Interface (MMC/SDIO2)
-
32-KHz synchronization timer
-
The TIPB bridges control the access rate to peripherals by inserting a
configurable amount of wait states into the strobe cycle of a peripheral register
access. The access factor bits of the TIPB control mode register (CMR) specify
the number of wait states of the strobe signal. The access rate to a peripheral
depends on the number of wait states used. Table 79 lists the equivalent
access rate for each of the possible number of wait states.
SPRU890A