Texas Instruments OMAP5910 Reference Manual page 178

DSP DMA
Table 66. DMA Source and Destination Parameters Register (DMACSDP)
Field Descriptions (Continued)
Bits Field
1−0 DATATYPE
178 DSP Subsystem
Value Description
Data type bits. DATATYPE indicates how data is to be accessed at the
source and at the destination of the channel. Note that the DMA
controller uses byte addresses for its accesses; each byte in data
space or I/O space has its own address. For information on how
addresses are updated between element transfers, see the
descriptions for the DSTAMODE bits and the SRCAMODE bits of
DMACCR, section 7.3.5.
00b 8-bit. The DMA controller makes 8-bit accesses at the source and at
the destination of the channel. The source and destination start
addresses have no alignment constraint:
Start address: XXXX XXXX XXXX XXXXb (X can be 0 or 1)
If you choose the automatic post increment addressing mode at the
source or the destination, the corresponding address is updated by an
increment of 1 after each element transfer.
Connection of a channel configured as 8-bit data type to the peripheral
port is not supported.
Internally, 8-bit data read requests from the DSP external memory are
converted to 16-bit data read requests by the EMIF. The appropriate
byte is fetched from this read request and placed in internal memory.
01b 16-bit. The DMA controller makes 16-bit accesses at the source and
at the destination. The source and destination start addresses must
each be on an even 2-byte boundary; the least significant bit (LSB)
must be 0:
Start address: XXXX XXXX XXXX XXX0b (X can be 0 or 1)
If you choose the automatic post increment addressing mode at the
source or the destination, the address is updated by an increment of
2 after each element transfer.
10b 32-bit. The DMA controller makes 32-bit accesses at the source and
at the destination. The source and destination start addresses must
be on an even 4-byte boundary; the 2 LSBs must be 0:
Start address: XXXX XXXX XXXX XX00b (X can be 0 or 1)
If you choose the automatic post increment addressing mode at the
source or the destination, the address is updated by an increment of
4 after each element transfer.
11b Reserved (do not use).
SPRU890A