Tipb Control Mode Register (Cmr) Field Descriptions; Dsp Side - Texas Instruments OMAP5910 Reference Manual

TI Peripheral Bus Bridges
Figure 92. TIPB Control Mode Register (CMR)

DSP Side

15
7 6
ACCESS_FACTOR1
RW-1
MPU Side
31
15
7 6
ACCESS_FACTOR1
R-0
†
The MPU core always reads this bit as a 0 when host-only mode is selected (see section 9.2.1).
Note: R = Read; W = Write; −n = Value after reset; -x = Value after reset is not defined.
Table 83. TIPB Control Mode Register (CMR) Field Descriptions
Bits Field
15−9 TIMEOUT
8−6 ACCESS_
FACTOR1
192 DSP Subsystem
TIMEOUT
RW-0x7F
5
ACCESS_FACTOR0
RW-1
Reserved
R-0
TIMEOUT
R-0x7F
5
ACCESS_FACTOR0
R-1
Value Description
This field determines the number of DSP subsystem clock cycles that
can elapse before the TIPB bridge module returns a bus-error
condition. The timeout period is determined as:
Timeout Period = TIMEOUT + 2
0−7 These bits set the number of wait states inserted when communicating
with peripherals as listed in Table 80 and Table 81.
3 2
CPU_
PRIORITY ERROR
RW-1
3 2
CPU_
PRIORITY ERROR
R-1
9 8
ACCESS_
FACTOR1
RW-1
1 0
BUS_ MPUI_
MODE
R-0 R-1
16
9 8
ACCESS_
FACTOR1
R-0
1 0
BUS_ MPUI_
MODE
R-0 † R-1
SPRU890A