Dsp Subsystem Interrupts - Texas Instruments OMAP5910 Reference Manual

DSP Subsystem Interrupts

11 DSP Subsystem Interrupts
11.1 Overview
204 DSP Subsystem
A number of interrupts can be generated inside and outside the DSP
subsystem. The DSP core is responsible for servicing these interrupts. This
section gives a brief overview of interrupt setup and handling for the DSP
subsystem. For more details on DSP subsystem interrupts, see the
OMAP5912 Multimedia Processor Interrupts Reference Guide (SPRU757) or
the OMAP5910 Multimedia Processor DSP Subsystem Interrupts Reference
Guide (SPRU923).
DSP core interrupts on OMAP devices are cascaded through a two levels of
interrupt handlers. A second-level interrupt controller(s) takes a number of
interrupts and generates a single interrupt to a first-level interrupt controller.
The first-level interrupt controller manages the interrupt(s) from the
second-level interrupt controller(s) and a number of other interrupts. The
first-level interrupt controller interfaces directly to the DSP core. Figure 96 and
Figure 97 show this process. The number of interrupt controllers varies across
OMAP devices, but the concept of cascading interrupts is the same.
SPRU890A