Omap5910 Level 2 Interrupt Mapping; Second Level Interrupts - Texas Instruments OMAP5910 Reference Manual

11.3

Second Level Interrupts

Table 93. OMAP5910 Level 2 Interrupt Mapping
Level 2
Mapping
Name
IRQ_0 MCBSP3_TX
IRQ_1 MCBSP3_RX
IRQ_2 MCBSP1_TX
IRQ_3 MCBSP1_RX
IRQ_4 UART2
IRQ_5 UART1
IRQ_6 MCSI1_TX
IRQ_7 MCSI1_RX
IRQ_8 MCSI2_TX
IRQ_9 MCSI2_RX
IRQ_10 MCSI1_FRAME_ER-
ROR_INT
IRQ_11 MCSI2_FRAME_ER-
ROR_INT
IRQ_12 −
IRQ_13 −
IRQ_14 −
IRQ_15 −
SPRU890A
OMAP devices include a second level of interrupt handlers which take a
number of peripheral interrupts and generate one or two interrupts to the first
level interrupt handler. For each interrupt, you must specify whether the
interrupt is edge or level sensitive.
On OMAP5910, the level 2 interrupt handler generates a single interrupt to
INT3 on the level 1 interrupt handler. The level 2.0 interrupt handler on
OMAP5912 generates a single interrupt to INT3 on the level 1 interrupt
handler, while level 2.1 generates a single interrupt to INT17. Table 93,
Table 94, and Table 95 detail the interrupt mapping for each device.
Required
Sensitivity
Setup
Edge
Edge
Edge
Edge
Level
Level
Level
Level
Level
Level
Level
Level
−
−
−
−
DSP Subsystem Interrupts
Function
McBSP #3 transmit interrupt
McBSP #3 receive interrupt
McBSP #1 transmit interrupt
McBSP #1 receive interrupt
UART #2 interrupt
UART #1 interrupt
MCSI #1 transmit interrupt
MCSI #1 receive interrupt
MCSI #2 transmit interrupt
MCSI #2 receive interrupt
MCSI #1 frame error interrupt
MCSI #2 frame error interrupt
Reserved, keep masked
Reserved, keep masked
Reserved, keep masked
Reserved, keep masked
DSP Subsystem 213