Receive Multicast/Broadcast/Promiscuous Channel Enable Register (Rxmbpenable); Receive Multicast/Broadcast/Promiscuous Channel Enable Register (Rxmbpenable) Field Descriptions - Texas Instruments TMS320DM646x User Manual

Ethernet Media Access Controller (EMAC) Registers

5.21 Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE)

The receive multicast/broadcast/promiscuous channel enable register (RXMBPENABLE) is shown in
Figure 61 and described in
Figure 61. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE)
31 30
Reserved RXPASSCRC
R-0 R/W-0
23 22
RXCSFEN RXCEFEN
R/W-0 R/W-0
15 14
Reserved
R-0
7 6
Reserved
R-0
LEGEND: R = Read only; R/W = Read/Write; -n = value after reset
Table 60. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE)
Bit Field
31 Reserved
30 RXPASSCRC
29 RXQOSEN
28 RXNOCHAIN
27-25 Reserved
24 RXCMFEN
23 RXCSFEN
102 Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)
Table 60.
29 28
RXQOSEN RXNOCHAIN
R/W-0 R/W-0
21 20
RXCAFEN
R/W-0
13 12
RXBROADEN
R/W-0
5 4
RXMULTEN
R/W-0
Field Descriptions
Value Description
0 Reserved
Pass receive CRC enable bit
0 Received CRC is discarded for all channels and is not included in the buffer descriptor packet
length field.
1 Received CRC is transferred to memory for all channels and is included in the buffer descriptor
packet length.
Receive quality of service enable bit
0 Receive QOS is disabled.
1 Receive QOS is enabled.
Receive no buffer chaining bit
0 Received frames can span multiple buffers.
1 The Receive DMA controller transfers each frame into a single buffer, regardless of the frame or
buffer size. All remaining frame data after the first buffer is discarded. The buffer descriptor buffer
length field will contain the entire frame byte count (up to 65535 bytes).
0 Reserved
Receive copy MAC control frames enable bit. Enables MAC control frames to be transferred to
memory. MAC control frames are normally acted upon (if enabled), but not copied to memory. MAC
control frames that are pause frames will be acted upon if enabled in MACCONTROL, regardless of
the value of RXCMFEN. Frames transferred to memory due to RXCMFEN will have the CONTROL
bit set in their EOP buffer descriptor.
0 MAC control frames are filtered (but acted upon if enabled).
1 MAC control frames are transferred to memory.
Receive copy short frames enable bit. Enables frames or fragments shorter than 64 bytes to be
copied to memory. Frames transferred to memory due to RXCSFEN will have the FRAGMENT or
UNDERSIZE bit set in their EOP buffer descriptor. Fragments are short frames that contain CRC /
align / code errors and undersized are short frames without errors.
0 Short frames are filtered.
1 Short frames are transferred to memory.
27
Reserved
R-0
19 18
Reserved
R-0
11 10
Reserved
R-0
3 2
Reserved
R-0
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25 24
RXCMFEN
R/W-0
16
RXPROMCH
R/W-0
8
RXBROADCH
R/W-0
0
RXMULTCH
R/W-0
SPRUEQ6 – December 2007
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