Serial Port Control Register (Spcr); Serial Port Control Register (Spcr) Field Descriptions - Texas Instruments TMS320C6201 Reference Manual

McBSP Interface Signals and Registers
Table 11–5. Serial Port Control Register (SPCR) Field Descriptions
Name Function
FRST Frame sync generator reset
FRST = 0: The frame sync generation logic is reset. Frame sync signal is not
FRST = 1: Frame sync signal is generated after eight CLKG clocks. All frame
GRST Sample rate generator reset
GRST = 0: Sample rate generator is reset.
GRST = 1: Sample rate generator is pulled out of reset; CLKG is driven accord-
RINTM Receive interrupt mode
RINTM = 00b: RINT driven by RRDY
RINTM = 01b: RINT generated by end-of-subframe in multichannel operation
RINTM = 10b: RINT generated by a new frame synchronization
RINTM = 11b: RINT generated by RSYNCERR
XINTM Transmit interrupt mode
XINTM = 00b: XINT driven by XRDY
XINTM = 01b: XINT generated by end-of-subframe in multichannel
XINTM = 10b: XINT generated by a new frame synchronization
XINTM = 11b: XINT generated by XSYNCERR
RSYNCERR Receive synchronization error
RSYNCERR = 0: No frame synchronization error
RSYNCERR = 1: Frame synchronization error detected by McBSP
XSYNCERR Transmit synchronization error
XSYNCERR = 0: No frame synchronization error
XSYNCERR = 1: Frame synchronization error detected by McBSP
XEMPTY Transmit shift register (XSR) empty
XEMPTY = 0: XSR is empty.
XEMPTY = 1: XSR is not empty.
11-8
generated by the sample rate generator.
counters are loaded with their programmed values.
ing to the programmed values in the sample rate generator register
(SRGR).
operation
Section
11.5.3
11.5.1.2
11.3.3
11.3.3
11.3.7.2
11.3.7.5
11.3.7.2
11.3.7.5
11.3.7.4