I 2 S Interrupt Enable Register - I2Sier - Holtek HT32F52342 User Manual

32-bit microcontroller with arm cortex-m0+ core
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32-Bit Arm
®
Cortex
®
-M0+ MCU
HT32F52342/HT32F52352
I
2
S Interrupt Enable Register – I2SIER
This register contains the corresponding I
Offset:
0x004
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
Reserved
RXOVIEN RXUDIEN RXFTLIEN Reserved
Type/Reset
RW
Bits
Field
[6]
RXOVIEN
[5]
RXUDIEN
[4]
RXFTLIEN
[2]
TXOVIEN
[1]
TXUDIEN
[0]
TXFTLIEN
Rev. 1.30
2
S interrupt enable bits.
30
29
28
22
21
20
14
13
12
6
5
4
0 RW
0 RW
Descriptions
RX FIFO Overflow Interrupt Enable
0: Disable
1: Enable
RX FIFO Underflow Interrupt Enable
0: Disable
1: Enable
RX FIFO Trigger Level Interrupt Enable
0: Disable
1: Enable
TX FIFO Overflow Interrupt Enable
0: Disable
1: Enable
TX FIFO Underflow Interrupt Enable
0: Disable
1: Enable
TX FIFO Trigger Level Interrupt Enable
0: Disable
1: Enable
642 of 656
27
26
Reserved
19
18
Reserved
11
10
Reserved
3
2
TXOVIEN
0
RW
0 RW
25
24
17
16
9
8
1
0
TXUDIEN TXFTLIEN
0 RW
0
September 28, 2018

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