I 2 S Clock Rate Generator; Figure 201. I S Clock Generator Diagram - Holtek HT32F52342 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52342/HT32F52352
I 2 S Clock Rate Generator
The main (I 2 S_MCLK) and bit clock (I
the I2SCDR register. The required I
rate desired, the format (stereo/mono) used, and the data size. The main clock rate (I
is generated using a fractional rate divider which is a divided down PCLK frequency of the I
Values of the numerator (X) and the denominator (Y) must be chosen to produce a frequency twice
that of the main clock (I
get the duty cycle of the output clock more even. The I
Figure 201. The equation for the fractional rate divider is:
Because the fractional rate divider is a fully digital implementation function, the divider output
clock transitions are synchronous with the input source clock. Therefore, the fractional rate divider
will generate some jitter with some divider settings. Users should make note of this phenomenon
when choosing the X and Y setup values. It is possible to avoid jitter entirely by choosing fractions
such that X divides evenly into Y. For example, 2/4, 2/6, 3/9, etc.
The tables below show the recommended setup values to reduce clock jitter for different source
clocks and sample rates.
PCLK
Figure 201. I 2 S Clock Generator Diagram
Rev. 1.30
2 S_BCLK) rates for the I
2 S bit clock rate setting depends on the desired audio sample
2 S_MCLK). The output frequency of the divider is divided by 2 in order to
I S_MCLK = 1/2 × PCLK × (X/Y), and X/Y ≤ 1, X = 1 ~ 255, Y = 1 ~ 255
2
I S_BCLK = I S_MCLK / (N+1), N = 0 ~ 255
2 2
I2S Clock Generator
X Y
8-bit Fractional
Rate Divider
& Fine-Tuning
Controller
629 of 656
2 S are determined by the values in
2 S clock generator block diagram is shown in
2 (N+1)
I2S Control
Logic
2 S_MCLK)
S.
2
I2S_MCLK
I2S_BCLK
I2S_WS
September 28, 2018