Channel 2 Output Configuration Register - Ch2Ocfr - Holtek HT32F54231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F54231/HT32F54241/HT32F54243/HT32F54253
Channel 2 Output Configuration Register – CH2OCFR
This register specifies the channel 2 output mode configuration.
Offset: 0x048
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
Reserved CH2IMAE
Type/Reset
Bits Field
[5] CH2IMAE
[4] CH2PRE
Rev. 1.00
30 29 28
22 21 20
14 13 12
6 5 4
CH2PRE
RW 0 RW
Descriptions
Channel 2 Immediate Active Enable
0: No action
1: Single pulse Immediate Active Mode is enabled
The CH2OREF signal will be forced to the compare matched level immediately
after an available trigger event occurs irrespective of the result of the
comparison between the CNTR and the CH2CCR values.
The effective duration ends automatically at the next overflow or underflow event.
Note: The CH2IMAE bit is available only if the channel 2 is configured to be operated
in the PWM mode 1 or PWM mode 2.
Channel 2 Capture/Compare Register (CH2CCR) Preload Enable
0: CH2CCR preload function is disabled.
The CH2CCR register can be immediately assigned a new value when the
CH2PRE bit is cleared to 0 and the updated CH2CCR value is used immediately.
1: CH2CCR preload function is enabled
The new CH2CCR value will not be transferred to its shadow register until the
update event occurs.
265 of 576
27 26
Reserved
19 18
Reserved
11 10
Reserved
3 2
Reserved CH2OM[2:0]
0 RW 0 RW
25 24
17 16
9 8
CH2OM[3]
RW 0
1 0
0 RW 0
January 28, 2022