Fujitsu FR60 Hardware Manual page 76

CHAPTER 3 CPU AND CONTROL UNITS
■ CCR (Condition Code Register)
The configuration of the condition code register (CCR) is shown below:
[Bit 5] Stack flag
This bit specifies the stack pointer to be used as R15.
Value
0
1
• Reset clears this bit to "0".
• Set this bit to "0" when executing a RETI instruction.
[Bit 4] Interrupt enable flag
This bit enables or disables a user interrupt request.
Value
0
1
• Reset clears this bit to "0".
[Bit 3] Negative flag
This bit indicates the sign when the operation result is regarded as an integer represented by its 2's
complement.
Value
0
1
• The initial value after reset is undefined.
58
7 6 5 4
- - S I
The system stack pointer (SSP) is used as R15.
When an EIT occurs, this bit is automatically set to "0".
(Note that the value saved on the stack is the value before it is cleared.)
The user stack pointer (USP) is used as R15.
User interrupt disabled.
When the INT instruction is executed, this bit is cleared to "0".
(Note that the value saved on the stack is the value before it is cleared.)
User interrupt enabled.
The mask processing of a user interrupt request is controlled by the value held in ILM.
Indicates that the operation result is a positive value.
Indicates that the operation result is a negative value.
3 2 1 0
N Z V C
Description
Description
Description
[Initial value]
--00XXXX
B