Fujitsu FR60 Hardware Manual page 389

ACS3 ACS2 ACS1
0 0 0
0 0 0
0 0 1
0 0 1
0 1 0
0 1 0
0 1 1
0 1 1
1 0 0
1 0 0
1 0 1
1 0 1
1 1 0
1 1 0
1 1 1
1 1 1
Note: Because the MB91F353A/351A/352A/353A do not have channels AN8, AN9, AN10, and AN11, the
corresponding channel settings are not allowed on the MB91F353A/351A/352A/353A.
[Bits 11 and 10] (unused)
These bits are not used.
[Bit 9] CREG
The CREG bit specifies the number of bits of the data to be stored as the result of A/D conversion.
[0: 10-bit mode]
The high-order two bits of the converted data are stored in the ADTHx register, and the low-order eight
bits are stored in the ADTLx register.
[1: 8-bit mode]
The high-order eight bits of the converted data are stored in the ADTLx register.
The CREG bit is cleared to "0" by a reset.
ACS0 Channel
0 AN0
1 AN1
0 AN2
1 AN3
0 AN4
1 AN5
0 AN6
1 AN7
0 AN8
1 AN9
0 AN10
1 AN11
0 -
1 -
0 -
1 -
Corresponding data register
ADTH0, ADTL0
ADAH1, ADTL1
ADTH2, ADTL2
ADTH3, ADTL3
ADTH0, ADTL0
ADAH1, ADTL1
ADTH2, ADTL2
ADTH3, ADTL3
ADTH0, ADTL0
ADAH1, ADTL1
ADTH2, ADTL2
ADTH3, ADTL3
-
-
-
-
Remarks
Setting not allowed
Setting not allowed
Setting not allowed
Setting not allowed
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