■ Timing of Clearing of the 16-bit Free-running Timer
The counter is cleared by a reset or by software or on a match with the compare clear register.
Clearing of the counter by a reset or by software is performed at the same time that the clearing occurs.
However, for clearing on a match with the compare clear register 0, the counter is cleared synchronized
with the count timing.
Figure 7.1-4 shows the timing of clearing the 16-bit free-running timer.
Figure 7.1-4 Timing of Clearing of the 16-bit Free-running Timer
Value of compare clear register
■ Timing of 16-bit Free-running Timer Counting
The 16-bit free-running timer counts up according to the input clock (internal or external clock). If an
external clock is selected, the falling edge (indicated by a down arrow) of the external clock is
synchronized with the system clock, then the 16-bit free-running timer counts up at the falling edge of the
internal count clock.
Figure 7.1-5 shows the timing of counting by the 16-bit free-running timer.
External clock input
Internal count clock
• If setting of the interrupt request flag and counter clearing occur at the same time, setting of the
interrupt request flag has priority over clearing of the counter and the clearing operation is
• If "1" is written to bit 2 (counter initialization bit [CLR]) of the control status register, the written
value is retained until the timing that clears the internal counter. The CLR bit is also cleared by the
same timing. If writing "1" to the CLR bit occurs at the same time as the timing that clears the
counter, writing "1" to the CLR bit has priority over clearing of the counter and the CLR bit remains
"1" until the next timing for clearing the counter.
• The counter clearing operation is valid only while the internal counter is operating (and the
internal prescaler is also operating). To clear the counter while the counter is stopped, write
to the timer count data register.
Figure 7.1-5 Timing of 16-bit Free-running Timer Counting
N + 1