Dma External Interface - Fujitsu FR60 Hardware Manual

16.6

DMA External Interface

This section describes the DMA external interface.
Note: The MB91F353A/351A/352A/353A do not have a DMA external interface.
■ Overview of DMA External Interface Operation
DMA ch0 to ch2 have DMA-dedicated pins (DREQ, DACK, and DEOP).
• DREQ
DREQ is a DMA transfer request input pin used to execute demand transfer. Input "1" to request
transfer.
• DACK
DACK becomes active ("L" output) when the DMA accesses external area through the external
interface.
• DEOP
DEOP becomes active ("L" output) in synchronization with the last access operation when all DMA
transfer operations have ended.
• IORD
IORD becomes active when the transfer direction I/O → memory is selected for fly-by transfer.
• IOWR
IOWR becomes active when the transfer direction memory → I/O is selected for fly-by transfer.
■ Examples of Operation (Simple Waveforms)
●
2-cycle transfer (external → external transfer and transfer count = 2)
Figure 16.6-1 shows a simple waveform for 2-cycle transfer (external → external transfer and transfer
count = 2).
Figure 16.6-1 Simple Waveform for 2-Cycle Transfer
(External → External Transfer and Transfer Count = 2)
A24 - A0
#RD1 #WR1
RD
WR
EOP
DACK
CS1
1 st write
1 st read
#RD2 #WR2
2 nd read
2 nd write
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