Fujitsu FR60 Hardware Manual page 423

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Send operation in modes 0, 1, and 2
TDRE is cleared when data is written to the SODR register. This bit is set when data is transferred to the
internal shift register and the next data can be written, causing an interrupt request to be generated for the
CPU.
If "0" is written to TXE of the SCR register (as well as RXE in mode 2) during a send operation, TDRE of
the SSR register is set to "1", disabling the UART send operation after the transmission shifter stops. The
device sends data written to the SODR register before transmission stops after "0" is written to the TXE of
the SCR register (as well as RXE in mode 2) during the send operation.
Figure 14.1-7 shows the timing for setting the TDRE bit in mode 0 or 1.
Figure 14.1-7 Timing for Setting TDRE (Modes 0 and 1)
Writing to SODR
TDRE
SO interrupt
SO output
ST: Start bit, D0 to D7: Data bits
SP: Stop bit, A/D: Address/data multiplexer
Figure 14.1-8 shows the timing for setting the TDRE bit in mode 2.
Figure 14.1-8 Timing for Setting TDRE (Mode 2)
Writing to SODR
TDRE
SO interrupt
SO output
Interrupt request to CPU
ST D0 D1 D2 D3 D4 D5 D6 D7 SP SP ST D0 D1 D2 D3
Interrupt request to CPU
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
A/D
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