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CHAPTER 3 CPU AND CONTROL UNITS
■ Normal and Synchronous Standby Operations
If "1" is set for Bit 8 (SYNCS bit) of the timebase counter control register (TBCR), synchronous standby
operation is enabled. In this case, simply writing to the STOP bit does not cause a transition to the stop
state. Instead, writing to the STOP bit and then reading the STCR register causes a transition to the stop
state.
If "0" is set for the SYNCS bit, normal standby operation is selected. In this case, simply writing to the
STOP bit causes a transition to the stop state.
If, in normal standby operation, the value set for the divide-by rate of the peripheral clock (CLKP) is larger
than the CPU clock (CLKB), many instructions are executed before writing to the STOP bit actually
occurs. Thus, after the write instruction to the STOP bit, the same number of NOP instructions as {5 +
(CPU clock divide-by rate/peripheral clock divide-by rate)} instructions or more must be inserted.
Otherwise, subsequent instructions are executed before the transition to the stop state.
In synchronous standby operation, the stop state occurs only after writing to the STOP bit actually occurs
and the reading of STCR register are completed. This is because the CPU uses the bus until the value read
from the STCR register is stored into the CPU. Thus, in any setting of relationship between divide-by rates
of the CPU clock (CLKB) and the peripheral clock (CLKP), insert only two NOP instructions after the
write instruction for the STOP bit and the read instruction for the STCR register to prevent any subsequent
instructions from being executed before transition to the stop state.
142

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