[Bit 8] INT (INTerrupt)
This bit is the transfer end interrupt request flag bit. For a read by a read modify instruction, "1" is
If this bit is set to "1", the SCL line is maintained at the "L" level. Write "0" to this bit to clear it and to
open the SCL line to transfer the next byte. In master mode, a repeated START or STOP condition is
This bit is cleared when the SCC bit or the MSS bit is set to "1".
Contention of SCC, MSS, and INT bits
If data is simultaneously written to the SCC, MSS, and INT bits, contention occurs between the
next-byte transfer, repeated START condition generation, and STOP condition generation. If this
situation occurs, the priorities are as follows:
1. Next-byte transfer and STOP condition generation
When the INT bit is set to "0" and the MSS bit is set to "0", writing of the MSS bit has
precedence and a STOP condition is generated.
2. Next-byte transfer and START condition generation
When "0" is written to the INT bit and "1" is written to the SCC bit, writing to the SCC bit has
precedence, a repeated START condition is generated, and the value of IDAR is sent.
3. Repeated START condition generation and STOP condition generation
When the SCC bit is set to "1" and the MSS bit is set to "0" at the same time, clearing of the
MSS bit has precedence. A STOP condition is generated and the I
4. When an instruction which generates a start condition is executed (the MSS bit is set to "1") at
the timing shown in Figure 15.2-1 and Figure 15.2-2 , arbitration lost detection (AL bit=1)
prevents an interrupt (INT bit=1) from being generated.
5. Condition 1 in which an interrupt (INT bit=1) upon detection of "AL bit=1" does not occur
Clears the transfer end interrupt request flag.
Has no meaning.
Transfer not ended, not the transfer target, or bus is idle.
This bit is set to "1" if a one-byte transfer that includes the acknowledge bit is
completed and the following conditions are met:
The interface was specified as a slave address.
A general call address was received.
Arbitration lost occurred.
If the interface is specified as a slave address, this bit is set at the end of slave
address reception that includes an acknowledge.
C interface enters slave
C Interface Register