Fujitsu FR60 Hardware Manual page 174

CHAPTER 3 CPU AND CONTROL UNITS
■ Detailed Explanation of the Peripheral Stop Control Registers
The bits of each register are described below.
When a bit of RSTOP0 to RSTOP3 (peripheral stop register) is "0", a clock is supplied to the
corresponding peripheral resource. Writing "1" to the bit stops supply of the clock to that peripheral
resource.
A reset (INIT) clears all bits and sets all peripheral resources to receive a clock.
●
Peripheral stop register 0 (RSTOP0)
Peripheral stop register 0 controls the supply of clock signals to the UART and the synchronous serial
interface.
The configuration of peripheral stop register 0 is shown below:
RSTOP0
bit
00000494
H
Bit
15
14
13
12
11
10
9
8
* : For the MB91F353A/351A/352A/353A, the settings of the ST05 and ST04 bits are disabled.
156
15 14 13
ST07 ST06 ST05* ST04*
Name
ST07 0: A clock signal is supplied to synchronous serial interface ch7 (initial
value).
1: Supply of the clock signal is stopped.
ST06 0: A clock signal is supplied to synchronous serial interface ch6 (initial
value).
1: Supply of the clock signal is stopped.
* 0: A clock signal is supplied to synchronous serial interface ch5 (initial
ST05
value).
1: Supply of the clock signal is stopped.
* 0: A clock signal is supplied to UART ch4/U-TIMER ch4 (initial value).
ST04
1: Supply of the clock signal is stopped.
ST03 0: A clock signal is supplied to UART ch3/U-TIMER ch3 (initial value).
1: Supply of the clock signal is stopped.
ST02 0: A clock signal is supplied to UART ch2/U-TIMER ch2 (initial value).
1: Supply of the clock signal is stopped.
ST01 0: A clock signal is supplied to UART ch1/U-TIMER ch1 (initial value).
1: Supply of the clock signal is stopped.
ST00 0: A clock signal is supplied to UART ch0/U-TIMER ch0 (initial value).
1: Supply of the clock signal is stopped.
12 11 10
ST03 ST02 ST01
Initial value
9 8
at INIT at RST
00
ST00
H
Access
xx
W
H