Fujitsu FR60 Hardware Manual page 299

■ Timer Control Status Register (TCCS)
The bit configuration of the timer control status register (TCCS) is shown below.
[Bit 7] ECLK
This bit is used to switch the count clock source for the 16-bit free-running timer between internal and
external sources.
Because the clock source is changed immediately after a value is written to the ECLK bit, the value of
this bit must be changed while the output compare and input capture operations are stopped.
ECLK
Notes:
• If the internal clock is selected, set the count clock using bits 1 and 0 (CLK1 and CLK0). The
count clock becomes the base clock. To input an external clock from the FRCK pin, set the
corresponding DDR bit to "0".
• The minimum pulse width required for the external clock is 2.T (T stands for the peripheral clock
machine cycle). If the external clock is specified and the output compare function is used,
compare match output and an interrupt occur at the next clock cycle. Therefore, to generate the
compare match output and interrupt, at least one clock pulse must be input after matching of
values occurs.
[Bit 6] IVF
This bit is the interrupt request flag for the 16-bit free-running timer.
This bit is set to "1" when the 16-bit free-running timer overflows or the counter is cleared because the
values of the counter and compare register 0 compare match depending on the mode setting.
An interrupt is generated if the interrupt request enable bit (bit 5 [IVFE]) is set.
The IVF bit is cleared by writing "0". Writing "1" to the IVF bit is ignored. If a read modify write
instruction is issued, "1" is always read from the IVF bit.
TCCS
bit
Address: 0000D7
H
Initial value
0 Internal clock source (initial value)
1 Input clock from external pin (FRCK)
IVF
0 Interrupt not requested (initial value)
1 Interrupt requested
7 6 5
ECLK IVF IVFE STOP MODE
R/W R/W R/W R/W
(0) (0) (0)
Clock selection
Interrupt request flag
4 3 2 1
CLR CLK1
R/W R/W R/W
(0) (0) (0) (0)
0
CLK0
R/W
(0)
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