Serial I/O Interface Registers - Fujitsu FR60 Hardware Manual

14.2.2

Serial I/O Interface Registers

This section describes the configuration and functions of the registers used by the
serial I/O interface.
■ Serial Mode Control Status Register (SMCS)
The bit configuration of the serial mode control status register (SMCS) is shown below.
SMCS
Address : 000024
000028
00002C
SMCS
Address : 000025
000029
00002D
*1: Only "0" can be written.
*2: Only "0" can be written. "0" is always read.
The serial mode control status register (SMCS) controls the operating mode of the serial I/O transfer. The
functions of the bits are explained below.
Note: The MB91F353A/351A/352A/353A do not have SIO ch5. (Settings of 000024
invalid.)
[Bits 15, 14, and 13] Shift clock selection bits (SMD2, SMD1, SMD0: Serial shift clock mode)
The shift clock selection bits are used to select the serial shift clock mode as shown below.
SMD2
0
0
0
0
1
1
1
1
15 14 13
SMD2 SMD1 SMD0
H
R/W R/W R/W
H
H
7 6 5
- - -
H
H
H
SMD1 SMD0
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
12 11 10
SIE SIR BUSY STOP
R/W R/W R/W R/W
*1
4 3 2
- MODE BDS
R/W R/W
φ=25MHz φ=20MHz
div=3 div=4
Setting not 2.5MHz
allowed
2.08MHz 1.25MHz
520kHz 312kHz
260kHz 156kHz
130kHz 78kHz
External shift clock mode
Reserved
Reserved
9 8 Initial value:
00000010
STRT
R/W
*2
1 0 Initial value:
----00--
- -
H
φ=10MHz
div=5
1MHz
500kHz
125kHz
62.5kHz
31.2kHz
B
B
and 000025 are
H
Divide-by
value
2
4
16
32
64
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