Fujitsu FR60 Hardware Manual page 550

CHAPTER 16 DMA CONTROLLER (DMAC)
■ FR30 Compatible Mode of DACK
The FR30-compatible mode of this DACK sets the DACK timing to the same timing as that of FR30
family DMA. Use the PFR register corresponding to the DACK pin to set FR30-compatible mode.
Match the PFR setting to the transfer mode (fly-by or 2-cycle) of the corresponding DMA channel.
Note:
When FR30-compatible mode is set for 2-cycle transfer, transfer is synchronized with RD or WR/
WRn. To use WR, set TYPE3-0 of the external interface ACR register to 0x1x to enable WR.
Figure 16.6-6 shows a setting example for transfer in 2-cycle transfer mode. Figure 16.6-7 shows a setting
example for transfer in fly-by transfer mode.
Setting Examples:
Figure 16.6-6 Setting Example for Transfer in 2-Cycle Transfer Mode
RD
DQMU/L
WR/WRn
DACK(AKxx=111)
DACK(AKxx=001) Setting not allowed for 2-cycle transfer
DACK(AKxx=010)
DACK(AKxx=011)
DACK(AKxx=100)
DACK(AKxx=101)
DACK(AKxx=110)
Figure 16.6-7 Setting Example for Transfer in Fly-by Transfer Mode
532
AKxx : The setting value of the PFR register corresponding to the DMA channel.
RD
DQMU/L
WR/WRn
IORD
IOWR
Same timing as chip select
DACK(AKxx=111)
DACK(AKxx=001)
DACK(AKxx=010) Setting not allowed for fly-by transfer
DACK(AKxx=011) Setting not allowed for fly-by transfer
DACK(AKxx=100) Setting not allowed for fly-by transfer
DACK(AKxx=101) Setting not allowed for fly-by transfer
DACK(AKxx=110) Setting not allowed for fly-by transfer
Memory -> I/O
AKxx : The setting value of the PFR register corresponding to the DMA channel.
Same timing as chip select
I/O -> memory Memory -> I/O I/O -> memory