*1: This is a test register. Access is not allowed.
*2: Immediately after release of a reset, the available internal RAM area is limited by the functions described in CHAPTER 19 "DATA
INTERNAL RAM/INSTRUCTION INTERNAL RAM ACCESS RESTRICTION FUNCTIONS". In addition, if the setting for
available area is rewritten, insert at least one NOP instruction immediately after that processing.
*3: The MB91F353A/351A/352A/353A do not have this register. Access is not allowed.
*4: The 16 low-order bits (DTC [15:0]) of DMACA0 to 4 cannot be byte-accessed.
*5: This register is accessed by mode vector fetch. It cannot be accessed during normal operation.
APPENDIX A I/O Map