Fujitsu FR60 Hardware Manual page 562

CHAPTER 17 FLASH MEMORY
[Bits 2 to 0] WTC2, WTC1, and WTC0 (wait cycle bits)
These bits control the wait status of flash memory.
WTC2 WTC1 WTC0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
• In a reset, the WTC2 bit is initialized to "0", the WTC1 bit is initialized to "1", and the WTC0 bit is
initialized to "1".
• For the MB91F355A/F353A/F356B/F357B, it becomes the above by the minimum operating supply
voltage and the operable wait count.
In addition, the operable wait count varies according to the setting state of the WE bit the FLCR
register.
544
VDD = 3.0V@50MHz
Wait
count
WE bit 0
- Setting not
allowed
1 Setting not
allowed
2 Operation
allowed
3 Operation
allowed
4 Operation
allowed
5 Operation
allowed
6 Operation
allowed
7 Operation
allowed
VDD = 2.7V@50MHz
WE bit 1 WE bit 0
Setting not Setting not
allowed allowed
Setting not Setting not
allowed allowed
Setting not Setting not
allowed allowed
Setting not Operation
allowed allowed
Operation Operation
allowed allowed
Operation Operation
allowed allowed
Operation Operation
allowed allowed
Operation Operation
allowed allowed
WE bit 1
Setting not
allowed
Setting not
allowed
Setting not
allowed
Setting not Initial value
allowed
Operation
allowed
Operation
allowed
Operation
allowed
Operation
allowed