Fujitsu FR60 Hardware Manual page 548

CHAPTER 16 DMA CONTROLLER (DMAC)
●
Fly-by transfer (I/O → memory transfer and transfer count = 3)
Figure 16.6-2 shows a simple waveform for fly-by transfer (I/O → memory transfer and transfer count =
3).
Figure 16.6-2 Simple Waveform for Fly-by Transfer (I/O → Memory Transfer and Transfer Count = 3)
●
Fly-by transfer (memory → I/O transfer and transfer count = 3)
Figure 16.6-3 shows a simple waveform for fly-by transfer (memory → I/O transfer and transfer count =
3).
Figure 16.6-3 Simple Waveform for Fly-by Transfer (Memory → I/O Transfer and Transfer Count = 3)
■ Timing of DREQx Pin Input
The DREQx pin is a DMA activation request signal. When the DREQx pin also functions as a port, use the
PFR register to enable DREQ input.
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Timing
1. Except for demand transfer, set edge detection as the DMA activation source. There are no
requirements regarding the rise/fall timing, but the DREQ signal retention time must be at least three
clock cycles. To request transfer again, input the request after DMA transfer has ended (request after
DEOP output). Requests input before DEOP output are sometimes ignored. Figure 16.6-4 shows a
DREQx edge request (2-cycle transfer).
2. For demand transfer, set level detection as the DMA activation source. There are no requirements
regarding the start of activation, but for stopping, synchronization with RD/WR of DMA transfer is
necessary. The sensing timing is the rise of MCLK of the last external access operation. Figure 16.6-5
shows a DREQx level request (2-cycle transfer).
530
A24 to A0 CPU
RD
WR
IORD
EOP
DACK
CS1
1 st fly-by
CPU read
A24 to A0
CPU
RD
WR
IOWR
EOP
DACK
CS1
st
CPU read 1 fly-by
#1 #2 #3
2 nd fly-by 3 rd fly-by
#2
#1 #3
nd rd
2 fly-by 3 fly-by