Fujitsu FR60 Hardware Manual page 544

CHAPTER 16 DMA CONTROLLER (DMAC)
MB91xxx
Read cycle
I-bus
D-bus
MB91xxx
Read cycle
I-bus
D-bus
MB91xxx
Read cycle
I-bus
D-bus
526
Figure 16.5-3 External Area → Internal I/O Area Transfer
External area => built-in I/O area transfer
DMAC
X-bus
Bus controller
Data buffer
F-bus
RAM I/O
Figure 16.5-4 Internal I/O Area → Internal RAM Area Transfer
Built-in I/O area => internal RAM area transfer
DMAC
X-bus
Bus controller
Data buffer
F-bus
RAM I/O
Figure 16.5-5 Internal RAM Area → External Area Transfer
Internal RAM area => external area transfer
DMAC
X-bus
Bus controller
Data buffer
F-bus
RAM I/O
MB91xxx
DMAC
Write cycle
I-bus
Bus controller
D-bus Data buffer
F-bus
RAM
MB91xxx
DMAC
Write cycle
I-bus
Bus controller
D-bus
Data buffer
F-bus
RAM
MB91xxx
DMAC
Write cycle
I-bus
Bus controller
D-bus
Data buffer
F-bus
RAM
X-bus
I/O
X-bus
I/O
X-bus
I/O