Flash Memory Wait Register (Flwc) - Fujitsu FR60 Hardware Manual

17.2.2

Flash Memory Wait Register (FLWC)

The flash memory wait register (FLWC) controls the wait status of flash memory access
in CPU mode.
■ Configuration of the Flash Memory Wait Register (FLWC)
The configuration of the flash memory wait register (FLWC) is shown below.
[Bits 7 and 6] Reserved: Reserved bits
Always set these bits to "0."
[Bits 5 and 4] FAC1 and FAC0
These bits control internal pulse generation for flash control. For the MB91F355A, MB91F353A,
MB91F356B and MB91F357B, these bits set the ATDIN/EQIN pulse width.
FAC1
0
0
1
1
• In a reset, the FAC1 bit is initialized to "0" and the FAC0 bit is initialized to "1".
• For the MB91F355A, MB91F353A, MB91F356B and MB91F357B, always set the FAC1 bit to "0" and
the FAC0 bit to "1".
[Bit 3] Reserved: Reserved bit
Always set this bit to "0."
Address : 00007004
H
Initial value→ (0)
FAC0 ATDIN
0 0.5 CLKB clock
1 1.0 CLKB clock
0 1.5 CLKB clock
1 2.0 CLKB clock
7 6 5 4
- - FAC1 FAC0
R R/W R/W R/W
(0) (0) (1)
EQIN
1.0 CLKB clock
1.5 CLKB clock
2.0 CLKB clock
2.5 CLKB clock
3 2 1
- WTC2 WTC1 WTC0
R/W R/W R/W R/W
(0) (0) (1) (1)
Setting not allowed
Initial value
Setting not allowed
Setting not allowed
0
543