Fujitsu FR60 Hardware Manual page 647

Flash Memory Wait Register
Configuration of the Flash Memory Wait Register
(FLWC) ............................................. 543
Flash Microcontroller Programmer
System Configuration of the Flash Microcontroller
Programmer........................................ 572
FLCR
Configuration of the Flash Control/Status Register
(FLCR) (CPU Mode)........................... 540
Flow
Flow of Data During 2-Cycle Transfer ............... 525
Flow of Data During Fly-By Transfer ................ 527
FLWC
Configuration of the Flash Memory Wait Register
(FLWC) ............................................. 543
Fly-By Transfer
Flow of Data During Fly-By Transfer ................ 527
Step/Block Transfer 2-Cycle Transfer Fly-by
Transfer ............................................. 500
FR
FR CPU Features ................................................. 2
FR30 Compatible Mode
FR30 Compatible Mode of DACK..................... 532
FR-CPU
FR-CPU Programming Mode
(16 Bits,Read/Write Enabled)............... 546
FR-CPU ROM Mode (32 Bits,Read only) .......... 545
Free-running Timer
Block Diagram of the 16-bit Free-running
Timer................................................. 279
Timing of 16-bit Free-running Timer Counting
.......................................................... 285
Timing of Clearing of the 16-bit Free-running
Timer................................................. 285
FRLR
FRLR: Instruction RAM Limit Control Register
(F-Bus RAM Limit Control Register)
.......................................................... 578
Fujitsu Standard Serial Onboard
Pins Used for Fujitsu Standard Serial Onboard
Writing .............................................. 569
Function
Functions of the DMACA0 to 4 Bits .................. 476
Functions of the DMACB0 to 4 Bits .................. 482
Functions of the DMACR Bits .......................... 490
Functions of the DMASA0 to 4 Bits and DMADA0 to
4 Bits ................................................. 488
G
General Control Register
Configuration of General Control Register 10
.......................................................... 310
Configuration of General Control Register 20
.......................................................... 313
General-Purpose Register
General-Purpose Registers...................................56
Generation
Generation of Internal Operating Clock ..............104
H
Halfword Access
Halfword Access ..............................................202
Handling
Handling of NC and Open Pins ............................33
Hardware Configuration
Hardware Configuration of the DMAC ...............472
Hardware Configuration of the Interrupt
Controller ...........................................324
Hardware Sequence Flag
Hardware Sequence Flag ...................................552
Harvard/Princeton Bus Converter
Harvard/Princeton Bus Converter.........................52
Hold Request Cancel Request
Hold Request Cancellation Request (HRLC: Hold
Request Cancel Request) ......................337
Hold Request Cancellation Request
Example of Using the Hold Request Cancellation
Request Function (HRCR)....................338
Hold Request Cancellation Request (HRLC: Hold
Request Cancel Request) ......................337
Hold Request Cancellation Request Register
Bit Configuration of the Hold Request Cancellation
Request Register (HRCL) .....................331
Hold Suppress Level Interrupt
NMI/Hold Suppress Level Interrupt Processing
..........................................................511
How to
How to Read the Instruction Lists ......................603
How to Specify Address ....................................559
How to Specify Sectors .....................................562
HRCL
Bit Configuration of the Hold Request Cancellation
Request Register (HRCL) .....................331
HRCR
Example of Using the Hold Request Cancellation
Request Function (HRCR)....................338
HRLC
Hold Request Cancellation Request (HRLC: Hold
Request Cancel Request) ......................337
I
I Flag
I Flag.................................................................74
I/O
2-Cycle Transfer (External -> I/O)
(TYP[3:0] = 0000
IOWR = 00 ) ......................................226
H
INDEX
, AWR = 0008 , and
B H
629