Fujitsu FR60 Hardware Manual page 658

INDEX
Serial Mode Register
Serial Mode Register (SMR) ............................. 390
Serial Output Data Register
Serial Input Data Register (SIDR)/Serial Output Data
Register (SODR) ................................. 394
Serial Programming Connection
Basic Configuration of MB91F355A/353A/356B
Serial Programming Connection ........... 568
Examples of Serial Programming Connections
.......................................................... 570
Notes of MB91F355A/F353A/F356B/F357B Serial
Programming Connections ................... 573
Serial Shift Data Register
Serial Shift Data Register (SDR)........................ 416
Serial Status Register
Serial Status Register (SSR) .............................. 395
SES
SIO Test Register (SES).................................... 416
Setting
Setting Initialization Reset (INIT) Clear
Sequence .............................................. 98
Setting of Temporary Stopping by Writing to the
Control Register (Set Independently for Each
Channel or all Channels
Simultaneously) .................................. 511
Setting the Divide-By Rate................................ 110
Setting the External Bus...................................... 33
Settings Initialization Reset (INIT)....................... 95
Setting Initialization
Wait Time after Setting Initialization ................. 106
Setting of CS -> RD/WR Setup
Setting of CS -> RD/WR Setup and of RD/WR -> CS
Hold (TYP[3:0]=0000
.......................................................... 212
Setting of RD/WR -> CS Hold
Setting of CS -> RD/WR Setup and of RD/WR -> CS
Hold (TYP[3:0]=0000
.......................................................... 212
Setting Register
Notes on Setting Registers................................. 475
Shift Clock
Shift Clock ...................................................... 419
Shift Operation
Shift Operation Start/Stop Timing and I/O
Timing ............................................... 421
SIDR
Serial Input Data Register (SIDR)/Serial Output Data
Register (SODR) ................................. 394
Simple Waveforms
Examples of Operation (Simple Waveforms) ...... 529
Simulator
Simulator Debugger............................................ 43
640
,AWR=000B )
B H
,AWR=000B )
B H
Simultaneous Occurrence
Simultaneous Occurrence of a DMA Transfer Request
and an External Hold Request .............. 507
Single Conversion Mode
Single Conversion Mode .................................. 376
Single-chip
Bus Mode 0 (Single-chip Mode).......................... 91
SIO
Block Diagram of the Serial I/O Interface (SIO)
......................................................... 412
Overview of Serial I/O Interface (SIO)
Operation ........................................... 419
Overview of the Serial I/O Interface (SIO) ......... 410
Serial I/O Interface (SIO) Registers ................... 411
SIO..................................................................... 4
SIO Test Register
SIO Test Register (SES) ................................... 416
Slave Address
10-bit Slave Address Mask Register (ITMK) ...... 458
10-bit Slave Address Register (ITBA)................ 457
7-bit Slave Address Mask Register (ISMK) ........ 461
7-bit Slave Address Register (ISBA).................. 460
Example of Slave Address and Data Transfer
......................................................... 468
Slave Address Mask ......................................... 465
Slave Address Detection
Slave Address Detection ................................... 465
Sleep
Return from Standby Mode (Sleep/Stop) ............ 338
Sleep Mode
Notes on DMA Transfer in Sleep Mode ............. 515
Sleep Mode ..................................................... 138
SMCS
Serial Mode Control Status Register (SMCS)
......................................................... 413
SMR
Serial Mode Register (SMR) ............................. 390
SODR
Serial Input Data Register (SIDR)/Serial Output Data
Register (SODR)................................. 394
Software Request
Software Request ............................................. 496
Software Reset
Software Reset (STCR: SRST Bit Writing) .......... 97
Source
Sources of an Oscillation Stabilization Wait ......... 99
Source Clock
Selection of Source Clock................................. 104
Source Oscillation Input
Source Oscillation Input at Power-on ................... 33
Specification
Specification of the -K lib Option when Character
String Operation Functions are Used....... 40