Operation of the 8/16-bit Up/Down Counters/Timers
This section describes the 8/16-bit up/down counter/timer operation
■ Selecting Counting Mode
The 8/16-bit up/down counters/timers have four counting modes. The CMS1 and CMS0 bits of the CCR
register are used to select the counting modes. Table 6.1-1 lists the values of the CMS1 and CMS0 bits and
corresponding counting modes.
Table 6.1-1 Selecting Timer Counting Mode
(a) Timer mode [down count]
In timer mode, the output of the internal prescaler is used for counting down. For the internal prescaler,
either two machine cycles or eight machine cycles can be selected with the CLKS bit of the CCRH register.
(b) Up/down counting mode
In up/down counting mode, counting up/down is performed by counting the input through external pin AIN
and BIN. The input through the AIN pin controls counting up and the input through the BIN pin controls
The inputs through the AIN pin and BIN pin are subject to edge-detected. The edge detection can be
selected by the CES1 and CES0 bits of the CCRH register. Table 6.1-2 lists the values of the CES1 and
CES0 bits and the corresponding detection edges.
Table 6.1-2 Selecting the Detection Edge
(c) Phase difference counting mode (two multiplication/four multiplication)
In phase difference counting mode, to count the phase difference between phase A and phase B of the
encoder output signal, detect the input level of the BIN pin at input edge detection of the AIN pin and
detect the input level of the AIN pin at input edge detection of the BIN pin.
Timer mode [down count]
Up/down counting mode
Phase difference counting mode, 2 multiplication
Phase difference counting mode, 4 multiplication
Disables the edge detection.
Detects rising edge.
Detects falling edge.
Detects both falling and rising edges.