Peripheral Circuits Of Clock Controller - Fujitsu FR60 Hardware Manual

3.10.7

Peripheral Circuits of Clock Controller

This section describes the peripheral circuit functions of the clock controller.
■ Timebase Counter
The clock controller has a 26-bit timebase counter that runs on the system base clock.
The timebase counter is used to measure the oscillation stabilization wait time in addition to having the
uses listed below (For more information about the oscillation stabilization wait time, see Section "3.9.4
Oscillation Stabilization Wait Time").
• Watchdog timer
The watchdog timer, which is used to detect a system runaway, measures time using the bit output of
the timebase counter.
• Timebase timer
The timebase timer generates an interval interrupt using output from the timebase counter.
●
Watchdog timer
The watchdog timer detects a runaway using output from the timebase counter. If a program runaway
results in a watchdog reset no longer being postponed for a specified interval, a settings initialization reset
(INIT) request is generated as a watchdog reset.
[Startup and interval setting of the watchdog timer]
The watchdog timer is started when the reset source register and the watchdog timer control register
(RSRR) are written to for the first time after a reset (RST).
At this time, the interval time of the watchdog timer is set in Bits 09 and 08 (WT1 and WT0 bits). Only
the time defined in this first write is valid as the interval time setting. Any further writing is ignored.
[Postponing a watchdog reset]
Once the watchdog timer is started, the program must write {A5
watchdog reset postpone register (WPR) periodically.
This operation initializes the watchdog reset generation flag.
[Generation of a watchdog reset]
The watchdog reset generation flag is set at the trailing edge of the timebase counter output of the
specified interval. If the flag has already been set when a trailing edge is detected at a second time, a
settings initialization reset (INIT) request is generated as a watchdog reset.
[Stopping the watchdog timer]
The watchdog timer, once started, cannot be stopped until an operation initialization reset (RST) occurs.
In the following states, when an operation initialization reset (RST) occurs, the watchdog timer is
stopped and remains inoperative until a program starts it.
• Operation initialization reset (RST) state
• Settings initialization reset (INIT) state
• Oscillation stabilization wait reset (RST) state
} and {5A } in this order to the
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