Fujitsu FR60 Hardware Manual page 175

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Peripheral stop register 1 (RSTOP1)
Peripheral stop register 1 controls the supply of clock signals to the reload timer and PPG.
The configuration of peripheral stop register 1 is shown below:
RSTOP1
bit 7
00000495
ST17
H
Bit Name
7 ST17
6 ST16
5
ST15
4 ST14
3
ST13
2 ST12
1
ST11
0 ST10
*: For the MB91F353A/351A/352A/353A, the settings of the ST15, ST13, and ST11 bits are disabled.
6 5 4
ST16 ST15* ST14 ST13*
0: A clock signal is supplied to reload timer ch3 (initial value).
1: Supply of the clock signal is stopped.
0: A clock signal is supplied to reload timer channels 0 to 2 (initial value).
1: Supply of the clock signal is stopped.
* 0: A clock signal is supplied to PPG ch5 (initial value).
1: Supply of the clock signal is stopped.
0: A clock signal is supplied to PPG ch4 (initial value).
1: Supply of the clock signal is stopped.
* 0: A clock signal is supplied to PPG ch3 (initial value).
1: Supply of the clock signal is stopped.
0: A clock signal is supplied to PPG ch2 (initial value).
1: Supply of the clock signal is stopped.
* 0: A clock signal is supplied to PPG ch1 (initial value).
1: Supply of the clock signal is stopped.
0: A clock signal is supplied to PPG ch0 (initial value).
1: Supply of the clock signal is stopped.
3 2 1 0
ST12 ST11* ST10
Initial value
at INIT at RST Access
00 xx
W
H H
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