CHAPTER 4 EXTERNAL BUS INTERFACE
Bit WREN: Write-enable setting (For this setting only, only a setting that is the same as that of
Bit LEND: Little endian setting
For the following ACR setting, the setting on the base setting area side is valid:
Bits [3:0]TYPE[3:0]: Access type setting
For the AWR settings, the settings on the mask setting area side are valid.
For the CHER settings, the settings on the mask setting area side are valid.
A mask setting area can be set for only part of another CS area (base setting area). You cannot set a mask
setting area for an area without a base setting area. In addition, the mask setting area must not be
duplicated. Be careful when setting the ASR and ACR:ASZ[3:0] bits.
The following restrictions apply to bits [3:0]TYP[3:0]:
• A write-enable setting cannot be implemented by a mask.
• Write-enable settings in the base CS area and the mask setting area must be identical.
• If write operations to a mask setting area are disabled, the area is not masked and operates as a
base CS area.
• If write operations to the base CS area are disabled but are enabled to the mask setting area, the
area has no base, resulting in malfunctions.
• The MB91350A series does not have a CS4 to CS7 pin. As a result, only the ACR:TYPE[3:0] =
1111 mask area setting is valid for CS areas 4 to 7.
• Set both ASR and ACR at the same time using word access. When accessing ASR and ACR
using half word, please set ACR after setting ASR.
the base setting area is allowed)