■ Word Alignment
An FR family program must be placed at an address that is a multiple of 2.
Bit 0 of the PC is set to "0" if the PC is updated when an instruction is executed.
Bit 0 can be set to "1" only if an odd-number address is specified as the branch address.
If Bit 0 is set to "1", however, Bit 0 is invalid and an instruction must be placed at the address that is a
multiple of 2.
No odd-number address exception exists.
When FR family data is accessed, forced alignment is applied as described below to the address based on
Halfword access: An address must be a multiple of 2. (The lowest-order bit is forcibly set to "0".)
During word or halfword data access, some of the bits in the result of calculating an effective address are
forcibly set to "0".
For example, in @(R13, Ri) addressing mode, the register before addition is used without change in the
calculation (even if the lowest-order bit is "1") and the low-order bits are masked. A register before
calculation is not masked.
[Example] LD @(R13, R2), R0
An address must be a multiple of 4. (The lowest-order 2 bits are forcibly set to "00".)
Lower 2 bits forcibly masked