CHAPTER 3 CPU AND CONTROL UNITS
■ Operation of the Watch Timer
Figure 3.12-2 shows the counter states at start of watch timer, switching to the subclock, and transition to
stop mode during operation with the subclock.
Figure 3.12-2 Counter States at Transition to Subclock or Stop Mode
Value of counter
- Timer clearance (WS1 and WS0 bits=1)
(other than 0)
- Interval time selection
(WS1 and WS0 bits = 11
- Change of interval time
(WS1 and WS0 bits = 10
- Switching from main clock to subclock
■ Precautions for Using the Watch Timer
Use the oscillation stabilization wait time as a reference value because the oscillation cycle is unstable
immediately after oscillation is started.
No watch interrupt is generated while subclock oscillation is stopped because the watch timer is stopped.
Do not stop subclock oscillation if it is necessary to use the watch timer for processing.
If a WIF flag setting request occurs at the same time as a zero-clearance request from the CPU, the WIF
flag setting request has priority and the zero-clearance request is ignored.
stabilization wait time
Cleared by interrupt routine
Instruction to enter stop mode
* : When the OSCD2 bit of STCR is set to 0 (oscillation is
not stopped in stop mode)