Peripheral Stop Control - Fujitsu FR60 Hardware Manual

Hide thumbs Also See for FR60:

Table of Contents

Peripheral Stop Control

Peripheral stop control reduces the amount of power consumed by the device by

stopping the supply of clocks to peripheral resources that are not being used.

Because supplying or stopping a clock can be set for each channel of each peripheral

resource, detailed settings appropriate for how resources are used can be made.

■ List of Peripheral Stop Control Registers

The configuration of the peripheral stop control registers is shown below:

*: For the MB91F353A/351A/352A/353A, the settings of bits ST05, ST04, ST15, ST13, ST11, ST27, and ST26 are disabled.

■ Block Diagram of Peripheral Stop Control

Figure 3.14-1 shows a block diagram of peripheral stop control.

Figure 3.14-1 Block Diagram of Peripheral Stop Control

Each resource clock

UART ch0 / U-TIMER ch0

UART ch1 / U-TIMER ch1

UART ch2 / U-TIMER ch2

Initial value

Mb91350a series