Fujitsu FR60 Hardware Manual page 496

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CHAPTER 16 DMA CONTROLLER (DMAC)

[Bits 28 to 24] IS4 to 0 (Input Select)*: Transfer Source Selection

These bits select the source of the transfer request as listed in the table below. Note that the software

transfer request by the STRG bit function is always valid regardless of the settings of these bits.

*: The MB91F353A/351A/352A/353A do not have external pins or an SI05 transfer source.

When reset: Initialized to "00000".

These bits are readable and writable.

If DMA start resulting from an interrupt from a peripheral function is set (IS=1xxxx), disable interrupts

from the selected peripheral function with the ICR register.

If demand transfer mode is selected, only IS[4:0]=01110, 01111 can be set. Starting by other sources is

Setting disabled

External pin (DREQ) HH level or

External pin (DREQ) LL level or

UART0 (receiving complete)

UART1 (receiving complete)

UART2 (receiving complete)

UART0 (sending complete)

UART1 (sending complete)

UART2 (sending complete)

External interrupt 0

External interrupt 1

Reload timer 0

Reload timer 1

Reload timer 2

External interrupt 2

Mb91350a series