Fujitsu FR60 Hardware Manual page 171

■ Operation of Clock Supply Function
The MB91350A uses a timebase counter to secure the oscillation stabilization wait time after INIT or stop
mode. On the other hand, the MB91350A uses the main clock oscillation stabilization wait timer to secure
the main clock oscillation stabilization wait time while the subclock is selected as the clock source. This is
because the main clock oscillation stabilization wait timer operates on the main clock regardless of the
clock source selection.
Use the following procedure to execute main clock oscillation stabilization wait from main clock
oscillation stop state during subclock operation:
1. Set the time required for main clock oscillation stabilization with the WT1 and WT0 bits, and clear the
counter to "0" (by writing the oscillation stabilization wait time to the WS1 and WS0 bits and "0" to the
WCL bit).
If it is necessary to perform processing after the end of oscillation stabilization wait with an interrupt,
initialize the interrupt flag (by writing "0" to the WIF and WIE bits).
2. Start main clock oscillation (by writing "1" to Bit 0 [OCSDS1 bit] of OSCR).
3. In the program, wait until the WIF flag is set to "1".
4. Make sure that the WIF flag has been set to "1", then perform the processing to be done after the end of
oscillation stabilization wait. If interrupts are enabled, an interrupt is generated when the WIF bit is set
to "1". Then, perform the processing to be done after the end of oscillation stabilization wait by an
interrupt routine. If it is necessary to switch the clock source from the subclock to main clock, switch
the clock source after making sure that the WIF bit has been set to "1" as described above. (If the clock
source is switched to the main clock before main clock oscillation is stabilized, an unstable clock is
supplied to the entire device and subsequent operation is unpredictable.)
■ Operation of the Main Clock Oscillation Stabilization Wait Timer
Figure 3.13-2 shows the counter states at the start of the main clock oscillation stabilization wait timer and
switching to the main clock.
Figure 3.13-2 Counter States at the Start of the Main Clock Oscillation Stabilization Wait Timer
and Switching to the Main Clock
7FFFFF
Value of counter
- Timer clearance (WCL bit = 1) (other than 0)
- Timer interval selection (WS1 and WS0 bits = 11
- Start of main clock oscillation
(OSCDS1 bit of OSCR = 0)
WIF (interrupt request)
WIE (interrupt mask)
Clock mode
H
Main clock oscillation
stabilization wait time
Subclock
- Switching from subclock to main clock
Cleared by interrupt
)
B
routine
Main clock
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