Fujitsu FR60 Hardware Manual page 567

■ Read/Reset Command
Set flash memory into read/reset mode.
The flash memory remains in reading state until another command is entered.
When the power is turned on, flash memory is automatically set to the read or reset state. In this case, data
can be read without a command of the automatic algorithm.
Upon returning to read mode after the time limit is exceeded, note that a read/reset command sequence can
be issued. Data is read from flash memory in the next read cycle.
■ Program (Write)
In CPU programming mode, data is basically written in half-word units. The write operation is performed
in four cycles of bus operation. The command sequence has two "unlock" cycles, which are followed by a
write setup command and a write data cycle. Writing to memory starts in the last write cycle.
After an automatic write algorithm command sequence was executed, it becomes unnecessary to control the
flash memory externally. The flash memory itself internally generates write pulses to check the margin of
the cells to which data is written. The data polling function compares bit 7 of the original data with bit 7 of
the written data, and if these bits are the same, the automatic write operation ends (see "■Hardware
Sequence Flag" in Section "17.4.2 Checking the Automatic Algorithm Operating Status"). The automatic
write operation then returns to the read mode and accepts no more write addresses. After that, the flash
memory requests the next valid address. In this manner, the data polling function indicates a write
operation in memory.
During a write operation, all commands written to the flash memory are ignored. If a hardware reset starts
during write operation, the data at the address for writing may become invalid.
Writing operations can be performed in any address sequence and outside of sector boundaries. However,
write operations cannot change a data item "0" to "1". If a "0" is overwritten with a "1", the data polling
algorithm either determines that the elements are defective, or that "1" has been written. In the latter case,
however, the respective data item is read as "0" in reset or read mode. A data item "0" can be changed to
"1" only after an erase operation.
■ Chip Erase
The chip erase command sequence ("erase all sectors simultaneously") is executed in six access cycles.
First, two "unlock" cycles are executed, then a "Setup" command is written. After two more "unlock"
cycles, the chip erase command is entered.
During the chip erase command sequence, the user does not have to write to flash memory before the erase
operation. When the automatic erase algorithm is executed, flash memory checks cell states by writing a
pattern of zeros before automatically erasing the contents of all cells (preprogram). In this operation, flash
memory does not have to be controlled externally.
The automatic erase operation starts with the write operation of the command sequence and ends when bit 7
is set to "1", where flash memory returns to the read mode. The chip erase time can be expressed as
follows: time for sector erase x number of all sectors + time for writing to the chip (preprogram).
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