Control Status Register (Adcs1) - Fujitsu FR60 Hardware Manual

12.2.1

Control Status Register (ADCS1)

The control status register (ADCS1) controls the A/D converter and indicates its status.
■ Bit Configuration of the Control Status Register (ADCS1)
The bit configuration of the control status register (ADCS1) is shown below.
Address : 000079
[Bit 7] BUSY (busy)
Read values
Value
Written values
Value
Do not start the A/D converter by software and forcibly stop it at the same time (by writing "1" to the
STAR bit and "0" to the BUSY bit).
If a read modify write instruction is issued, "1" is always read from the BUSY bit. The BUSY bit is
cleared to "0" by a reset.
bit 7 6
BUSY INT INTE
H
0 0
R/W R/W R/W
0 A/D converter stopped
1 A/D converter operating
0 Forcible stopping of A/D converter
1 Invalid
5 4 3 2
- STS1 STS0
0 - 0 0
- R/W R/W
Meaning
Meaning
1 0
STAR Reserved ADCS1
<− Initial value
0 0
<− Bit attribute
R/W R/W
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