Fujitsu FR60 Hardware Manual page 231

■ DMA Fly-by Transfer (I/O → Memory) (TYP[3:0] = 0000
51 )
H
Figure 4.5-9 shows DMA fly-by transfer (I/O → memory).
• No wait setting in memory side
Basic cycle
MCLK
A[23:0]
AS
CSn
WRn
D[31:16]
IORD
• Setting "1" for the HLD bit of the IOWR0 to 3 registers enables the I/O read cycle to be extended by
one cycle.
• Setting bits IW[3:0], IW[13:10], and IW[23:20] of the IOWR0 to 3 registers enables 0 to 15 wait cycles
to be inserted.
• If wait is also set on the memory side (AWR[15:12] is not "0"), the larger value is used as the wait cycle
after comparison with the I/O wait (IW[3:0], IW[13:10], and IW[23:20] bits).
Figure 4.5-9 DMA Fly-by Transfer (I/O → Memory)
I/O wait I/O wait
cycle cycle
, AWR = 0008
B
I/O idle
cycle
Basic cycle
, and IOWR =
H
I/O wait I/O hold
cycle wait
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