Fujitsu FR60 Hardware Manual page 213

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8-bit bus width
Figure 4.4-9 shows the access operations for bus width of 8 bits.
(A) Word access
(a) PA1/PA0="00"
(1) Output A1/A0="00"
(2) Output A1/A0="01"
(3) Output A1/A0="10"
(4) Output A1/A0="11"
MSB LSB
00
(1)
01
(2)
10
(3)
(4) 11
8bit
(B) Halfword access
(a) PA1/PA0="00"
(1) Output A1/A0="00"
(2) Output A1/A0="01"
00
(1)
01
(2)
10
11
(C) Byte access
(a) PA1/PA0="00"
(1) Output A1/A0="00"
00
(1)
01
10
11
Figure 4.4-9 8-bit Bus Width Access
(b) PA1/PA0="01"
(1) Output A1/A0="00"
(2) Output A1/A0="01"
(3) Output A1/A0="10"
(4) Output A1/A0="11"
00
(1)
01
(2)
10
(3)
(4) 11
(b) PA1/PA0="01"
(1) Output A1/A0="00"
(2) Output A1/A0="01"
00
(1)
01
(2)
10
11
(b) PA1/PA0="01"
(1) Output A1/A0="01"
00
01
(1)
10
11
(c) PA1/PA0="10"
(1) Output A1/A0="00"
(2) Output A1/A0="01"
(3) Output A1/A0="10"
(4) Output A1/A0="11"
00
(1)
01
(2)
10
(3)
(4) 11
(c) PA1/PA0="10"
(1) Output A1/A0="10"
(2) Output A1/A0="11"
00
01
10
(1)
11
(2)
(c) PA1/PA0="10"
(1) Output A1/A0="10"
00
01
10
(1)
11
(d) PA1/PA0="11"
(1) Output A1/A0="00"
(2) Output A1/A0="01"
(3) Output A1/A0="10"
(4) Output A1/A0="11"
00
(1)
01
(2)
10
(3)
(4) 11
(d) PA1/PA0="11"
(1) Output A1/A0="10"
(2) Output A1/A0="11"
00
01
10
(1)
11
(2)
(d) PA1/PA0="11"
(1) Output A1/A0="11"
00
01
10
11
(1)
195