Fujitsu FR60 Hardware Manual page 654

INDEX
Power Supply
Power Supply Pins ............................................. 32
Power-On
Power-on........................................................... 33
Source Oscillation Input at Power-on ................... 33
Wait Time after Power-On ................................ 106
PPG
Block Diagram of the PPG Timer (Overall
Configuration and One Channel)........... 300
Examples of Methods Used to Perform All-L and
All-H PPG Output ............................... 319
Registers of the PPG Timer ............................... 299
PPG Cycle Setting Register
Configuration of PPG Cycle Setting Register
(PCSR)............................................... 307
PPG Duty Setting Register
Configuration of PPG Duty Setting Register
(PDUT) .............................................. 308
PPG Timer
Characteristics of PPG Timer ............................ 298
PPG Timer Registers ........................................ 302
PPG Timer Register
Configuration of PPG Timer Register (PTMR)
.......................................................... 309
PPG Timer Registers ........................................ 302
Precaution
Precautions ...................................................... 314
Precautions for Using the Watch Timer .............. 148
Precautions on the Debuggers.............................. 36
Precautions on Using the Little-Endian Area......... 37
Precautions on Using the Main Clock Oscillation
Stabilization Wait Timer ...................... 154
Prefetch
Basic Conditions for Starting External Access Using
Prefetch
.......................................................... 218
Burst Length Setting and Prefetch Efficiency
.......................................................... 219
Clearing/Updating the Prefetch Buffer................ 220
Optional Clear and Temporary Stopping of a Prefetch
Access................................................ 219
Prefetch............................................................. 35
Reading from the Prefetch Buffer ...................... 220
Unit for One Prefetch Access Operation ............. 219
Prefetch-enabled Area
Restrictions on Prefetch-enabled Areas............... 221
Priority
Priority Among Channels.................................. 516
Priority of EIT Causes to Be Accepted ................. 84
Priority Decision
Priority Decision .............................................. 332
Procedure
Procedure for Setting the External Bus
Interface ............................................. 230
636
Program
Program (Write)............................................... 549
Program Counter
PC (Program Counter) ........................................ 61
Program Status
PS (Program Status) ........................................... 57
PS
PS (Program Status) ........................................... 57
PS Register
Notes of PS Register .......................................... 35
PTMR
Configuration of PPG Timer Register (PTMR)
......................................................... 309
Pull-up
Pull-up Control .................................................. 34
Pull-up Control Register
Pull-up Control Registers (PCR)........................ 236
Pull-up Resistor
I/O Ports With Pull-up Resistors........................ 232
Pulse Width
Minimum Effective Pulse Width of the DREQ Pin
Input. ................................................. 518
Q
Quartz Oscillation Circuit
Quartz Oscillation Circuit ................................... 32
R
RAM
2-Cycle Transfer
(The Timing is the Same for Internal RAM
-> External I/O and RAM and for External
I/O and RAM -> Internal RAM.)
(TYP[3:0] = 0000
) ..................................... 225
IOWR = 00
H
Data Internal RAM/Instruction Internal RAM Access
Restriction Function Registers.............. 576
DRLR: Data RAM Limit Control Register
(D-Bus RAM Limit Control Register)
......................................................... 577
FRLR: Instruction RAM Limit Control Register
(F-Bus RAM Limit Control Register)
......................................................... 578
Internal RAM .................................................... 35
Operation of the Data Internal RAM/
Instruction Internal RAM Access Restriction
Functions ........................................... 579
RCR
Reload/Compare Register 0/1 (RCR 0/1)............ 258
RD
CS -> RD/WR Setup
(TYP[3:0] =0101
, AWR = 0008 , and
B H
, AWR=100B ) ....... 217
B H