Fujitsu FR60 Hardware Manual page 145

Note:
An upper-limit frequency for the operation is set for each clock. If the combination of source clock
selected, PLL multiply-by rate setting, and divide-by rate setting results in a frequency exceeding this
upper-limit frequency, operation is unpredictable. Be extremely careful of the order in which you
change the settings when selecting the source clock.
If the setting in this register is changed, the new divide-by rate takes effect for the clock rate following the
one during which the setting was made.
[Bits 7 to 4] T3, T2, T1, T0 (clkT divide select 3 to 0)
These bits are the clock divide-by rate setting bits of the external bus clock (CLKT).
Set the clock divide-by rate of the external extended bus interface clock (CLKT).
The values written to these bits determine the divide-by rate (clock frequency) for the base clock of the
external extended bus interface clock. Select the divide-by rate from the 16 types listed in the table
below.
The upper-limit frequency for operation is 25 MHz. Do not set a divide-by rate that results in a
frequency exceeding this limit.
T3 T2 T1
0 0 0
0 0 0
0 0 1
0 0 1
0 1 0
0 1 0
0 1 1
0 1 1
... ... ...
1 1 1
φ: Frequency of the system base clock
• These bits are initialized to "0000" by a reset (INIT).
• These bits are readable and writable.
[Bits 3 to 0] (reserved bits)
These bits are reserved.
T0 Clock divide-by rate
φ
0
φ × 2 (divided by 2)
1
φ × 3 (divided by 3)
0
φ × 4 (divided by 4)
1
φ × 5 (divided by 5)
0
φ × 6 (divided by 6)
1
φ × 7 (divided by 7)
0
φ × 8 (divided by 8)
1
... ...
φ × 16 (divided by 16)
1
Clock frequency: if the source oscillation is
12.5[MHz] and the PLL is multiplied by 4
50 [MHz] (initial value)
25 [MHz]
16.7 [MHz]
12.5 [MHz]
10 [MHz]
8.33 [MHz]
7.01 [MHz]
6.25 [MHz]
...
3.13 [MHz]
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