Fujitsu FR60 Hardware Manual page 141

[Bits 9, 8] CLKS1, CLKS0 (CLocK source Select)
These bits set the clock source that will be used by the FRex core.
The values written to these bits determine the clock source, which can be selected from the three types
listed in the table below:
While bit 9 (CLKS1) is set to "1", the value of bit 8 (CLKS0) cannot be changed.
To select the subclock in the post-INIT state, first write "01" and then write "11".
Note:
From subclock source X0A/X1A, the source oscillation input with the frequency divided by 2 cannot
be selected. In addition, immediately after writing "01", insert at least one NOP instruction.
CLKS1
0
0
1
1
• These bits are initialized to "00" by a reset (INIT).
• These bits are readable and writable.
Cannot be changed
"00" → "11"
"01" → "10"
"10" → "01" or "11"
"11" → "00" or "10"
CLKS0
0 Source oscillation input from X0/X1 divided by 2 (initial value)
1 Source oscillation input from X0/X1 divided by 2
0 Main PLL
1 Subclock
Can be changed
"00" → "01" or "10"
"01" → "11" or "00"
"10" → "00"
"11" → "01"
Clock source setting
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