Fujitsu FR60 Hardware Manual page 503
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- Hardware manual (636 pages) ,
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[Bit 22] SADR (Source-ADdr.-reg. Reload): Transfer source address register reload specification
This bit controls reloading of the transfer source address register for the corresponding channel.
If this bit enables the reload operation, the transfer source address register value is restored to its initial
value after the transfer is completed.
If reloading of the counter is disabled, a single shot operation occurs. In single shot operation, operation
stops after the transfer is completed even if reload is specified in the address register. The address
register value also stops in this case while the initial value is being reloaded.
If this bit disables the reload operation, the address register value when the transfer is completed is the
address to be accessed next to the final address. (When address increment is specified, the next address
is an incremented address.)
SADR
0
Disables transfer source address register reloading. (initial value)
1
Enables transfer source address register reloading.
•
When reset: Initialized to "0".
•
This bit is readable and writable.
[Bit 21] DADR (Dest.-ADdr.-reg. Reload): Transfer destination address register reload specification
This bit controls reloading of the transfer destination address register for the corresponding channel.
If this bit enables reloading, the transfer destination address register value is restored to its initial value
after the transfer is completed.
The details of other functions are the same as those described for Bit22 (SADR).
DADR
0
Disables transfer destination address register reloading. (initial value)
1
Enables transfer destination address register reloading.
•
When reset: Initialized to "0".
•
This bit is readable and writable.
[Bit 20] ERIE (ERror Interrupt Enable): Error interrupt output enable
This bit controls the occurrence of an interrupt for termination after an error occurs. The nature of the error
that occurred is indicated by DSS2 to "0". Note that an interrupt occurs only for specific termination
causes and not for all termination causes. (Refer to bits DSS2-0.)
ERIE
0
Disables error interrupt request output. (initial value)
1
Enables error interrupt request output.
•
When reset: Initialized to "0".
•
This bit is readable and writable.
Function
Function
Function
485
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