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Operation Of The Serial I/o Interface (sio) - Fujitsu FR60 Hardware Manual

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14.2.3

Operation of the Serial I/O Interface (SIO)

The serial I/O interface (SIO) consists of a serial mode control status register (SMCS)
and a serial shift data register (SDR) and is used to input and output 8-bit serial data.
■ Overview of Serial I/O Interface (SIO) Operation
For output, the bit contents of the serial shift data register (SDR) are outputted via a serial output pin (SO5
to SO7) in synchronization with the falling edge of the serial shift clock (external or internal clock). For
input, the bits of serial data are inputted via a serial input pin (SI5 to SI7) to the serial shift data register
(SDR) in synchronization with the rising edge of the serial shift clock. The shift direction (MSB-first mode
or LSB-first mode) can be specified by the bit direction select (BDS) bit of the serial mode control status
register (SMCS).
When serial data transfer ends, the serial I/O interface stops or enters a state in which it stands by for
reading of or writing to the serial shift data register. The state after transfer depends on the status of the
MODE bit of the serial mode control status register (SMCS).
To restore the SIO transfer operation from the stop or standby state, follow the relevant procedure below.
1. To resume operation from the stop state, write "0" to the STOP bit and "1" to the STRT bit. (The STOP
and STRT bits can be set simultaneously.)
2. To resume operation from the serial shift data register R/W standby state, read or write to the data
register.
■ Shift Clock
There are two modes of shift clock: internal or external shift clock. These two modes are selected by setting
the SMCS
To switch the modes, ensure that serial I/O transfer is stopped. To check whether the serial I/O transfer is
stopped, read the BUSY bit.
Internal shift clock mode
In internal shift clock mode, data transfer is based on the internal clock, and a shift clock with a 50% duty
ratio can be outputted from the SCK pin as the synchronization timing output.
Data is transferred at a rate of one bit per clock pulse. The transfer speed is expressed as follows:
"A" indicates the clock division ratio specified by the SMD bits of the SMCS register, and is one of the
following:
Transfer speed(s) =
2
(φ/div)/2, (φ/div)/2
, (φ/div)/2
A
Internal clock machine cycle (Hz)
4
5
, (φ/div)/2
, (φ/div)/2
6
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