CHAPTER 4 EXTERNAL BUS INTERFACE
The external bus interface controller contains a prefetch buffer consisting of 16 × 8 bits.
If the PSUS bit of the TCR register is "0" and read access to an area to which the PFEN
bit of the ACR register is set to "1" occurs, the subsequent address is prefetched and
then stored in the prefetch buffer.
If the stored address is accessed from the internal bus, the look-ahead data in the
prefetch buffer is returned without external access being performed. This can reduce
the wait time for successive accesses to the external bus areas.
■ Basic Conditions for Starting External Access Using Prefetch
External bus access using prefetch occurs when the following conditions are met:
The PSUS bit of the TCR register is "0".
Neither sleep mode nor stop mode is set.
Read access by the external bus to a chip select area for which prefetch is enabled has been performed.
DMA access and read access by a read modified write system instruction, however, are excluded.
No external bus access request (external bus area access to an area for which prefetch is not enabled or
DMA transfer with an external bus area) other than the prefetch access has occurred.
The part of the prefetch buffer for the next operation of capturing the prefetch access is completely
While the above conditions are met, the prefetch access will continue. If external bus area access to an
area for which prefetch is not enabled occurs after prefetch access, prefetch access to the area for which
prefetch is enabled will continue as long as the prefetch buffer clear conditions are not met.
For an access that mixes multiple prefetch-enabled areas and multiple prefetch-disabled areas, the prefetch
buffer always holds data of the prefetch-enabled area accessed last. Since, in this case, access to prefetch-
disabled areas does not affect the prefetch buffer state at all, data in the prefetch buffer is not wasted even if
prefetch-disabled data access and prefetch-enabled instruction fetch are mixed.