Fujitsu FR60 Hardware Manual page 148

CHAPTER 3 CPU AND CONTROL UNITS
[Suspending the watchdog timer (automatic postponement)]
If program operation stops on the CPU, the watchdog reset generation flag is initialized and generation
of a watchdog reset is postponed. Stopping of program operation specifically refers to the following
statuses:
• Sleep state
• Stop state
• Oscillation stabilization wait RUN state
• During a break taken when the emulator debugger or monitor debugger is being used
• Period from execution of INTE instruction to execution of RETI instruction
• Step trace trap (per - instruction break taken by setting the T flag in the PS register to "1")
• Instruction cache control registers (ISIZE, ICHCR): Data to cache memory in RAM mode
If the timebase counter is cleared, the watchdog reset generation flag is initialized at the same time,
postponing generation of a watchdog reset.
A watchdog reset may not be generated in the above situation caused by the system running out of control.
In that case, please reset (INIT) by external INIT terminal.
●
Timebase timer
The timebase timer generates an interval interrupt using output from the timebase counter. This timer is
appropriate for measurements that require a relatively long time (for example, a maximum interval of {base
clock x 2
If the trailing edge of the timebase counter output for the specified interval is detected, a timebase timer
interrupt request is generated.
[Startup and interval settings of the timebase timer]
For the timebase timer, the interval time is set in Bits 13-11 (TBC2, TBC1, and TBC0 bits) of the
timebase counter control register (TBCR).
The trailing edge of the timebase counter output for the specified interval is always detected.
Thus, after setting the interval time, clear Bit 15 (TBIF bit) and then set Bit 14 (TBIE bit) to "1" to
enable output of an interrupt request.
Before changing the interval time, set Bit 14 (TBIE bit) to "0" to disable interrupt request output. Since
the timebase counter always counts regardless of these settings, before enabling interrupts, clear the
timebase counter to obtain an accurate interval interrupt time. Otherwise, an interrupt request may be
generated immediately after an interrupt is enabled.
[Clearing of the timebase counter due to a program]
If {A5
the timebase counter are cleared to "0" immediately after {5A
between writing of {A5
written, {A5
If the timebase counter is cleared, the watchdog reset generation flag is initialized at the same time,
postponing generation of a watchdog reset.
130
27
} cycles such as for the PLL lock wait time or a subclock oscillation stabilization wait time.
} and {5A } are written in this order to the timebase counter clear register (CTBR), all bits of
H H
} and {5A
H
} must be written again before {5A
H
}. However, if data other than {5A
H
} is written. Otherwise, no clear operation occurs.
H
} is written. There is no time limit
H
} is written after {A5
H
} is
H