Fujitsu FR60 Hardware Manual page 196

CHAPTER 4 EXTERNAL BUS INTERFACE
[Bit 3] W03 (WR0 to WR1 Output Timing Selection)
The WR0 to WR1 output timing setting selects whether to use write strobe output as an asynchronous
strobe or synchronous write enable. The asynchronous strobe setting corresponds to normal memory/IO.
The synchronous enable setting corresponds to clock-synchronized memory/IO (such as the memory in
an ASIC).
W03
0
1
If synchronous write enable (W03 bit of AWR is "0") is used, operations are as follows:
• The timing of synchronous write enable output assumes that the output is captured by the rising edge of
MCLK output of an external memory access clock. This timing is different from the asynchronous
strobe output timing.
• The WR0 to WR1 terminal output asserts synchronous write enable output at the timing at which AS
pin output is asserted. For a write to an external bus, the synchronous write enable output is L. For a
read from an external bus, the synchronous write enable output is "H".
• Write data is output from the external data output pin at the clock cycle at which synchronous write
enable output is asserted.
• Read strobe output (RD) functions as an asynchronous read strobe regardless of the setting of the WR0
to WR1 output timing. Use it as is for controlling the data I/O direction.
If synchronous write enable output is used, the following restrictions apply:
Do not make the following additional wait settings:
CS → RD/WR setup (Always set "0" for the W01 bit of AWR)
•
• First access wait cycle setting (Always set 0000
• Do not make the following access type settings (TYPE3-0 bits in the ACR register (bits 3 to "0"))
• Address/data multiplex bus setting (Always set "0" for the TYPE2 bit in the ACR register)
• Setting to use WR0 to WR1 as a write strobe (Always set "0" for the TYPE1 bit of ACR)
• RDY input enable setting (Always set "0" for the TYPE0 bit of ACR)
• For synchronous write enable output, always set "1" (00
length.
[Bit 2] W02 (Address → CS Delay)
The address → CS delay setting is made when a certain type of setup is required for the address when
CS falls or CS edges are needed for successive accesses to the same chip select area.
Set the address and set the delay from AS output to CS0 to CS3 output.
W02
0
1
178
WR0 to WR1 output timing selection
MCLK synchronous write enable output (valid from AS=L)
Asynchronous write strobe output (normal operation)
Address → CS delay
Delay
No delay
for the W15 to W12 bits of AWR)
B
for bits BST1 to 0 bits of ACR) as the burst
B