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INDEX
Data Direction Registers (DDR) ........................ 235
Data Internal RAM/Instruction Internal RAM Access
Restriction Function Registers .............. 576
Data Register (IDAR) ....................................... 462
Delayed Interrupt Module Register (DICR: Delayed
Interrupt Module Register) ................... 354
Detailed Explanation of the Peripheral Stop Control
Registers ............................................ 156
Details of the Interrupt Controller Registers ........ 328
Details of the Registers for the External Interrupt and
NMI Controller ................................... 344
Detection Result Register (BSRR) ..................... 359
DMAC Interrupt Source Clear Register (SRCL)
.......................................................... 418
DRLR: Data RAM Limit Control Register
(D-Bus RAM Limit Control Register)
.......................................................... 577
Explanation of the Main Clock Oscillation
Stabilization Wait Timer Register ......... 150
External Interrupt and NMI Controller
Registers ............................................ 342
FRLR: Instruction RAM Limit Control Register
(F-Bus RAM Limit Control Register)
.......................................................... 578
General-Purpose Registers .................................. 56
2
I
C Interface Registers...................................... 441
Initial Values and Functions of the Port Function
Registers (PFRs) ................................. 238
Input Capture Control Registers
(ICS01 and ICS23) .............................. 428
Input Capture Data Register (IPCP0 to IPCP3)
.......................................................... 428
Input Capture Module Registers......................... 426
Interrupt Controller Registers ............................ 325
Interrupt Level Mask (ILM) Register ................... 74
List of External Bus Interface Registers.............. 166
List of Peripheral Stop Control Registers ............ 155
List of Registers of the 8/16-bit Up/Down
Counters/Timers.................................. 248
Mapping of Interrupt Control Register (ICR) ........ 75
Mode Register (MODR) ..................................... 92
Multiply & Divide Register ................................. 63
Notes of PS Register........................................... 35
Notes on Setting Registers................................. 475
Oscillation Control Register (OSCCR) ............... 128
Output Compare Module Registers .................... 432
Output Control Register (OCS0 to OCS7)........... 434
Overview of Flash Memory Registers ................ 539
Overview of the A/D Converter Registers........... 364
Overview of the Data Registers
(ADTHx and ADTLx) ......................... 375
Overview of the DMAC Registers ..................... 473
2
Overview of the I
C Interface Registers.............. 444
Port Data Registers (PDR)................................. 234
Port Function Registers (PFR) ........................... 237
PPG Timer Registers ........................................ 302
Pull-up Control Registers (PCR) ........................ 236
638
Recommended ADCT Register Value................ 374
Register for the Delayed Interrupt Module.......... 353
Register Overview of External Bus Interface ...... 167
Registers of the PPG Timer............................... 299
Reload Register (UTIMR) ................................ 271
Reload/Compare Register 0/1 (RCR 0/1)............ 258
Reset Source Register/Watchdog Timer Control
Register (RSRR) ................................. 112
SCR (System Condition Code Register) ............... 60
Serial Control Register (SCR) ........................... 391
Serial I/O Interface (SIO) Registers ................... 411
Serial I/O Prescaler Control Register (CDCR)
......................................................... 417
Serial Input Data Register (SIDR)/Serial Output Data
Register (SODR)................................. 394
Serial Mode Control Status Register (SMCS)
......................................................... 413
Serial Mode Register (SMR) ............................. 390
Serial Shift Data Register (SDR) ....................... 416
Serial Status Register (SSR).............................. 395
Setting of Temporary Stopping by Writing to the
Control Register (Set Independently for Each
Channel or all Channels
Simultaneously) .................................. 511
SIO Test Register (SES) ................................... 416
Standby Control Register (STCR)...................... 114
Table Base Register (TBR) ................................. 79
TBR (Table Base Register) ................................. 61
Timebase Counter Clear Register (CTBR).......... 119
Timebase Counter Control Register (TBCR) ...... 117
Timer Control Status Register (TCCS) ............... 281
Timer Data Register (TCDT) ............................ 280
Transfer Count Registers and Reload Operation
......................................................... 505
UART Registers .............................................. 388
Up/Down Count Register 0/1 (UDCR 0/1) ......... 258
U-TIMER Control Register (UTIMC)................ 272
U-TIMER Registers ......................................... 269
U-TIMER Registers (UTIM)............................. 270
Watch Timer Control Register........................... 144
Watchdog Reset Postpone Register (WPR)......... 124
Writing Data to the Up/Down Count Register
(UDCR) ............................................. 264
Releasing
Releasing the Bus Right.................................... 228
Reload
Reload and Compare Functions ......................... 261
Up/Down Counting with an Arbitrary Width
when the Reload and Compare Functions are
Started ............................................... 262
Reload Operation
Reload Operation ............................................. 501
Transfer Count Registers and Reload Operation
......................................................... 505
Reload Register
Reload Register (UTIMR) ................................ 271

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